/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef AO_SUBCTRL_REG_OFFSET_H
#define AO_SUBCTRL_REG_OFFSET_H

/* AO_SUBCTRL Base address of Module's Register */
#define AO_SUBCTRL_BASE                       (0x0)

/* AO_SUBCTRL Registers' Definitions */
#define AO_SUBCTRL_SC_TIMEOUT_INFO_REG                    (AO_SUBCTRL_BASE + 0x100)
#define AO_SUBCTRL_SC_I2C4_CFG_REG                        (AO_SUBCTRL_BASE + 0x104)
#define AO_SUBCTRL_SC_I2C5_CFG_REG                        (AO_SUBCTRL_BASE + 0x108)
#define AO_SUBCTRL_SC_I2C6_CFG_REG                        (AO_SUBCTRL_BASE + 0x10C)
#define AO_SUBCTRL_SC_I2C9_CFG_REG                        (AO_SUBCTRL_BASE + 0x110)
#define AO_SUBCTRL_SC_SPI5_CTRL_REG                       (AO_SUBCTRL_BASE + 0x120)
#define AO_SUBCTRL_SC_SEC_WDOG_CLK_SEL_REG                (AO_SUBCTRL_BASE + 0x130)
#define AO_SUBCTRL_SC_WDOG0_CLK_SEL_REG                   (AO_SUBCTRL_BASE + 0x134)
#define AO_SUBCTRL_SC_WDOG1_CLK_SEL_REG                   (AO_SUBCTRL_BASE + 0x138)
#define AO_SUBCTRL_SC_WDOG2_CLK_SEL_REG                   (AO_SUBCTRL_BASE + 0x13C)
#define AO_SUBCTRL_SC_WDOG3_CLK_SEL_REG                   (AO_SUBCTRL_BASE + 0x140)
#define AO_SUBCTRL_SC_WDOG4_CLK_SEL_REG                   (AO_SUBCTRL_BASE + 0x144)
#define AO_SUBCTRL_SC_WDOG5_CLK_SEL_REG                   (AO_SUBCTRL_BASE + 0x148)
#define AO_SUBCTRL_SC_SMMU_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x300)
#define AO_SUBCTRL_SC_SMMU_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x304)
#define AO_SUBCTRL_SC_I2C4_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x308)
#define AO_SUBCTRL_SC_I2C4_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x30C)
#define AO_SUBCTRL_SC_I2C5_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x310)
#define AO_SUBCTRL_SC_I2C5_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x314)
#define AO_SUBCTRL_SC_I2C6_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x318)
#define AO_SUBCTRL_SC_I2C6_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x31C)
#define AO_SUBCTRL_SC_I2C9_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x320)
#define AO_SUBCTRL_SC_I2C9_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x324)
#define AO_SUBCTRL_SC_SPI_ICG_EN_REG                      (AO_SUBCTRL_BASE + 0x328)
#define AO_SUBCTRL_SC_SPI_ICG_DIS_REG                     (AO_SUBCTRL_BASE + 0x32C)
#define AO_SUBCTRL_SC_SMBUS_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x330)
#define AO_SUBCTRL_SC_SMBUS_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x334)
#define AO_SUBCTRL_SC_GPIO_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x338)
#define AO_SUBCTRL_SC_GPIO_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x33C)
#define AO_SUBCTRL_SC_UART_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x340)
#define AO_SUBCTRL_SC_UART_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x344)
#define AO_SUBCTRL_SC_GPIO8_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x348)
#define AO_SUBCTRL_SC_GPIO8_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x34C)
#define AO_SUBCTRL_SC_SYSCNT_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x350)
#define AO_SUBCTRL_SC_SYSCNT_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x354)
#define AO_SUBCTRL_SC_PMBUS0_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x358)
#define AO_SUBCTRL_SC_PMBUS0_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x35C)
#define AO_SUBCTRL_SC_PMBUS1_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x360)
#define AO_SUBCTRL_SC_PMBUS1_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x364)
#define AO_SUBCTRL_SC_PMCTRL_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x368)
#define AO_SUBCTRL_SC_PMCTRL_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x36C)
#define AO_SUBCTRL_SC_PMPWM_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x370)
#define AO_SUBCTRL_SC_PMPWM_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x374)
#define AO_SUBCTRL_SC_8K_ICG_EN_REG                       (AO_SUBCTRL_BASE + 0x378)
#define AO_SUBCTRL_SC_8K_ICG_DIS_REG                      (AO_SUBCTRL_BASE + 0x37C)
#define AO_SUBCTRL_SC_WDOG0_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x380)
#define AO_SUBCTRL_SC_WDOG0_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x384)
#define AO_SUBCTRL_SC_WDOG1_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x388)
#define AO_SUBCTRL_SC_WDOG1_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x38C)
#define AO_SUBCTRL_SC_WDOG2_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x390)
#define AO_SUBCTRL_SC_WDOG2_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x394)
#define AO_SUBCTRL_SC_WDOG3_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x398)
#define AO_SUBCTRL_SC_WDOG3_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x39C)
#define AO_SUBCTRL_SC_WDOG4_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x3A0)
#define AO_SUBCTRL_SC_WDOG4_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x3A4)
#define AO_SUBCTRL_SC_WDOG5_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x3A8)
#define AO_SUBCTRL_SC_WDOG5_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x3AC)
#define AO_SUBCTRL_SC_TIMER0_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x3B0)
#define AO_SUBCTRL_SC_TIMER0_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x3B4)
#define AO_SUBCTRL_SC_TIMER1_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x3B8)
#define AO_SUBCTRL_SC_TIMER1_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x3BC)
#define AO_SUBCTRL_SC_GICD_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x3C0)
#define AO_SUBCTRL_SC_GICD_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x3C4)
#define AO_SUBCTRL_SC_ITS_ICG_EN_REG                      (AO_SUBCTRL_BASE + 0x3C8)
#define AO_SUBCTRL_SC_ITS_ICG_DIS_REG                     (AO_SUBCTRL_BASE + 0x3CC)
#define AO_SUBCTRL_SC_MBIGEN_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x3D0)
#define AO_SUBCTRL_SC_MBIGEN_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x3D4)
#define AO_SUBCTRL_SC_LP_TIMER1_ICG_EN_REG                (AO_SUBCTRL_BASE + 0x3D8)
#define AO_SUBCTRL_SC_LP_TIMER1_ICG_DIS_REG               (AO_SUBCTRL_BASE + 0x3DC)
#define AO_SUBCTRL_SC_LP_TIMER2_ICG_EN_REG                (AO_SUBCTRL_BASE + 0x3E0)
#define AO_SUBCTRL_SC_LP_TIMER2_ICG_DIS_REG               (AO_SUBCTRL_BASE + 0x3E4)
#define AO_SUBCTRL_SC_LP_TIMER3_ICG_EN_REG                (AO_SUBCTRL_BASE + 0x3E8)
#define AO_SUBCTRL_SC_LP_TIMER3_ICG_DIS_REG               (AO_SUBCTRL_BASE + 0x3EC)
#define AO_SUBCTRL_SC_SEC_TIMER_ICG_EN_REG                (AO_SUBCTRL_BASE + 0x3F0)
#define AO_SUBCTRL_SC_SEC_TIMER_ICG_DIS_REG               (AO_SUBCTRL_BASE + 0x3F4)
#define AO_SUBCTRL_SC_SEC_WDOG_ICG_EN_REG                 (AO_SUBCTRL_BASE + 0x3F8)
#define AO_SUBCTRL_SC_SEC_WDOG_ICG_DIS_REG                (AO_SUBCTRL_BASE + 0x3FC)
#define AO_SUBCTRL_SC_IPC_S_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x400)
#define AO_SUBCTRL_SC_IPC_S_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x404)
#define AO_SUBCTRL_SC_IPC_NS_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x408)
#define AO_SUBCTRL_SC_IPC_NS_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x40C)
#define AO_SUBCTRL_SC_TRNG_ICG_EN_REG                     (AO_SUBCTRL_BASE + 0x410)
#define AO_SUBCTRL_SC_TRNG_ICG_DIS_REG                    (AO_SUBCTRL_BASE + 0x414)
#define AO_SUBCTRL_SC_TIMER2_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x418)
#define AO_SUBCTRL_SC_TIMER2_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x41C)
#define AO_SUBCTRL_SC_TIMER3_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x420)
#define AO_SUBCTRL_SC_TIMER3_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x424)
#define AO_SUBCTRL_SC_LP_TIMER0_ICG_EN_REG                (AO_SUBCTRL_BASE + 0x428)
#define AO_SUBCTRL_SC_LP_TIMER0_ICG_DIS_REG               (AO_SUBCTRL_BASE + 0x42C)
#define AO_SUBCTRL_SC_LSADC_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x430)
#define AO_SUBCTRL_SC_LSADC_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x434)
#define AO_SUBCTRL_SC_PAD_DB_ICG_EN_REG                   (AO_SUBCTRL_BASE + 0x438)
#define AO_SUBCTRL_SC_PAD_DB_ICG_DIS_REG                  (AO_SUBCTRL_BASE + 0x43C)
#define AO_SUBCTRL_SC_DJTAG_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x440)
#define AO_SUBCTRL_SC_DJTAG_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x444)
#define AO_SUBCTRL_SC_FUNC_MBIST_ICG_EN_REG               (AO_SUBCTRL_BASE + 0x448)
#define AO_SUBCTRL_SC_FUNC_MBIST_ICG_DIS_REG              (AO_SUBCTRL_BASE + 0x44C)
#define AO_SUBCTRL_SC_PROBE_ICG_EN_REG                    (AO_SUBCTRL_BASE + 0x450)
#define AO_SUBCTRL_SC_PROBE_ICG_DIS_REG                   (AO_SUBCTRL_BASE + 0x454)
#define AO_SUBCTRL_SC_ITS_RESET_REQ_REG                   (AO_SUBCTRL_BASE + 0x4C8)
#define AO_SUBCTRL_SC_ITS_RESET_DREQ_REG                  (AO_SUBCTRL_BASE + 0x4CC)
#define AO_SUBCTRL_SC_MBIGEN_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0x4D0)
#define AO_SUBCTRL_SC_MBIGEN_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0x4D4)
#define AO_SUBCTRL_SC_GICD_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0x4D8)
#define AO_SUBCTRL_SC_GICD_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0x4DC)
#define AO_SUBCTRL_SC_I2C4_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xA00)
#define AO_SUBCTRL_SC_I2C4_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xA04)
#define AO_SUBCTRL_SC_I2C5_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xA08)
#define AO_SUBCTRL_SC_I2C5_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xA0C)
#define AO_SUBCTRL_SC_I2C6_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xA10)
#define AO_SUBCTRL_SC_I2C6_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xA14)
#define AO_SUBCTRL_SC_I2C9_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xA18)
#define AO_SUBCTRL_SC_I2C9_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xA1C)
#define AO_SUBCTRL_SC_SPI_RESET_REQ_REG                   (AO_SUBCTRL_BASE + 0xA20)
#define AO_SUBCTRL_SC_SPI_RESET_DREQ_REG                  (AO_SUBCTRL_BASE + 0xA24)
#define AO_SUBCTRL_SC_SMBUS_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xA28)
#define AO_SUBCTRL_SC_SMBUS_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xA2C)
#define AO_SUBCTRL_SC_GPIO_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xA30)
#define AO_SUBCTRL_SC_GPIO_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xA34)
#define AO_SUBCTRL_SC_UART_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xA38)
#define AO_SUBCTRL_SC_UART_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xA3C)
#define AO_SUBCTRL_SC_GPIO8_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xA40)
#define AO_SUBCTRL_SC_GPIO8_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xA44)
#define AO_SUBCTRL_SC_APB_SUBCTRL_RESET_REQ_REG           (AO_SUBCTRL_BASE + 0xA48)
#define AO_SUBCTRL_SC_APB_SUBCTRL_RESET_DREQ_REG          (AO_SUBCTRL_BASE + 0xA4C)
#define AO_SUBCTRL_SC_SYSCNT_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xA50)
#define AO_SUBCTRL_SC_SYSCNT_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xA54)
#define AO_SUBCTRL_SC_PMCTRL_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xA60)
#define AO_SUBCTRL_SC_PMCTRL_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xA64)
#define AO_SUBCTRL_SC_PMBUS0_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xA68)
#define AO_SUBCTRL_SC_PMBUS0_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xA6C)
#define AO_SUBCTRL_SC_PMBUS1_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xA70)
#define AO_SUBCTRL_SC_PMBUS1_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xA74)
#define AO_SUBCTRL_SC_PMPWM_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xA78)
#define AO_SUBCTRL_SC_PMPWM_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xA7C)
#define AO_SUBCTRL_SC_8K_RESET_REQ_REG                    (AO_SUBCTRL_BASE + 0xA80)
#define AO_SUBCTRL_SC_8K_RESET_DREQ_REG                   (AO_SUBCTRL_BASE + 0xA84)
#define AO_SUBCTRL_SC_WDOG0_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xA88)
#define AO_SUBCTRL_SC_WDOG0_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xA8C)
#define AO_SUBCTRL_SC_WDOG1_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xA90)
#define AO_SUBCTRL_SC_WDOG1_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xA94)
#define AO_SUBCTRL_SC_WDOG2_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xA98)
#define AO_SUBCTRL_SC_WDOG2_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xA9C)
#define AO_SUBCTRL_SC_WDOG3_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xAA0)
#define AO_SUBCTRL_SC_WDOG3_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xAA4)
#define AO_SUBCTRL_SC_WDOG4_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xAA8)
#define AO_SUBCTRL_SC_WDOG4_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xAAC)
#define AO_SUBCTRL_SC_WDOG5_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xAB0)
#define AO_SUBCTRL_SC_WDOG5_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xAB4)
#define AO_SUBCTRL_SC_TIMER0_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xAB8)
#define AO_SUBCTRL_SC_TIMER0_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xABC)
#define AO_SUBCTRL_SC_TIMER1_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xAC0)
#define AO_SUBCTRL_SC_TIMER1_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xAC4)
#define AO_SUBCTRL_SC_TIMER2_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xAC8)
#define AO_SUBCTRL_SC_TIMER2_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xACC)
#define AO_SUBCTRL_SC_TIMER3_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xAD0)
#define AO_SUBCTRL_SC_TIMER3_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xAD4)
#define AO_SUBCTRL_SC_LP_TIMER0_RESET_REQ_REG             (AO_SUBCTRL_BASE + 0xAD8)
#define AO_SUBCTRL_SC_LP_TIMER0_RESET_DREQ_REG            (AO_SUBCTRL_BASE + 0xADC)
#define AO_SUBCTRL_SC_LP_TIMER1_RESET_REQ_REG             (AO_SUBCTRL_BASE + 0xAE0)
#define AO_SUBCTRL_SC_LP_TIMER1_RESET_DREQ_REG            (AO_SUBCTRL_BASE + 0xAE4)
#define AO_SUBCTRL_SC_LP_TIMER2_RESET_REQ_REG             (AO_SUBCTRL_BASE + 0xAE8)
#define AO_SUBCTRL_SC_LP_TIMER2_RESET_DREQ_REG            (AO_SUBCTRL_BASE + 0xAEC)
#define AO_SUBCTRL_SC_LP_TIMER3_RESET_REQ_REG             (AO_SUBCTRL_BASE + 0xAF0)
#define AO_SUBCTRL_SC_LP_TIMER3_RESET_DREQ_REG            (AO_SUBCTRL_BASE + 0xAF4)
#define AO_SUBCTRL_SC_SEC_TIMER_RESET_REQ_REG             (AO_SUBCTRL_BASE + 0xAF8)
#define AO_SUBCTRL_SC_SEC_TIMER_RESET_DREQ_REG            (AO_SUBCTRL_BASE + 0xAFC)
#define AO_SUBCTRL_SC_SEC_WDOG_RESET_REQ_REG              (AO_SUBCTRL_BASE + 0xB00)
#define AO_SUBCTRL_SC_SEC_WDOG_RESET_DREQ_REG             (AO_SUBCTRL_BASE + 0xB04)
#define AO_SUBCTRL_SC_IPC_S_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xB08)
#define AO_SUBCTRL_SC_IPC_S_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xB0C)
#define AO_SUBCTRL_SC_IPC_NS_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xB10)
#define AO_SUBCTRL_SC_IPC_NS_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xB14)
#define AO_SUBCTRL_SC_TRNG_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xB18)
#define AO_SUBCTRL_SC_TRNG_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xB1C)
#define AO_SUBCTRL_SC_BISR_RESET_REQ_REG                  (AO_SUBCTRL_BASE + 0xB38)
#define AO_SUBCTRL_SC_BISR_RESET_DREQ_REG                 (AO_SUBCTRL_BASE + 0xB3C)
#define AO_SUBCTRL_SC_PAD_DB_RESET_REQ_REG                (AO_SUBCTRL_BASE + 0xB40)
#define AO_SUBCTRL_SC_PAD_DB_RESET_DREQ_REG               (AO_SUBCTRL_BASE + 0xB44)
#define AO_SUBCTRL_SC_DJTAG_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xB48)
#define AO_SUBCTRL_SC_DJTAG_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xB4C)
#define AO_SUBCTRL_SC_FUNC_MBIST_RESET_REQ_REG            (AO_SUBCTRL_BASE + 0xB50)
#define AO_SUBCTRL_SC_FUNC_MBIST_RESET_DREQ_REG           (AO_SUBCTRL_BASE + 0xB54)
#define AO_SUBCTRL_SC_LSADC_RESET_REQ_REG                 (AO_SUBCTRL_BASE + 0xB58)
#define AO_SUBCTRL_SC_LSADC_RESET_DREQ_REG                (AO_SUBCTRL_BASE + 0xB5C)
#define AO_SUBCTRL_SC_CHAIN_ERR_CLR_REG                   (AO_SUBCTRL_BASE + 0x1100)
#define AO_SUBCTRL_SC_CHAIN_ERR_INTMASK_REG               (AO_SUBCTRL_BASE + 0x1104)
#define AO_SUBCTRL_SC_CHAIN_ERR_INT_STATUS_REG            (AO_SUBCTRL_BASE + 0x1108)
#define AO_SUBCTRL_SC_DISPATCH_ERRRSP_REG                 (AO_SUBCTRL_BASE + 0x2000)
#define AO_SUBCTRL_SC_GPIO_SYN_EN_REG                     (AO_SUBCTRL_BASE + 0x2004)
#define AO_SUBCTRL_SC_GPIO8_SYN_EN_REG                    (AO_SUBCTRL_BASE + 0x2008)
#define AO_SUBCTRL_SC_NOCMT_IRQ_REG                       (AO_SUBCTRL_BASE + 0x2120)
#define AO_SUBCTRL_SC_NOCMT_IRQ_INT_MASK_REG              (AO_SUBCTRL_BASE + 0x2124)
#define AO_SUBCTRL_SC_NOCMT_IRQ_STATUS_REG                (AO_SUBCTRL_BASE + 0x2128)
#define AO_SUBCTRL_SC_NOCMT_IRQ_RST_EN_REG                (AO_SUBCTRL_BASE + 0x212C)
#define AO_SUBCTRL_SC_NOCMT_IRQ_SEL_REG                   (AO_SUBCTRL_BASE + 0x2130)
#define AO_SUBCTRL_SC_USB_NFE_PULSE_WIDTH_REG             (AO_SUBCTRL_BASE + 0x2140)
#define AO_SUBCTRL_SC_CMD_DELY_DEFINE_REG                 (AO_SUBCTRL_BASE + 0x2350)
#define AO_SUBCTRL_SC_TP_MEM_CTRL_REG                     (AO_SUBCTRL_BASE + 0x3200)
#define AO_SUBCTRL_SC_SP_MEM_CTRL_REG                     (AO_SUBCTRL_BASE + 0x3204)
#define AO_SUBCTRL_SC_MEM_POWER_MODE_REG                  (AO_SUBCTRL_BASE + 0x3208)
#define AO_SUBCTRL_SC_ASYNC_FIFO_EMPTY_CLAMP_REG          (AO_SUBCTRL_BASE + 0x3260)
#define AO_SUBCTRL_SC_BUS_NUM_REG                         (AO_SUBCTRL_BASE + 0x3300)
#define AO_SUBCTRL_SC_CFG_BUS_WAIT_REG                    (AO_SUBCTRL_BASE + 0x3310)
#define AO_SUBCTRL_AUTOLF_FORCE_BUSY_REG                  (AO_SUBCTRL_BASE + 0x3400)
#define AO_SUBCTRL_AUTOLF_FORCE_IDLE_REG                  (AO_SUBCTRL_BASE + 0x3404)
#define AO_SUBCTRL_AUTOLF_IDLE_IN_TH_REG                  (AO_SUBCTRL_BASE + 0x3408)
#define AO_SUBCTRL_AUTOLF_CFG_EN_REG                      (AO_SUBCTRL_BASE + 0x340C)
#define AO_SUBCTRL_AUTOLF_IDLE_STATUS_REG                 (AO_SUBCTRL_BASE + 0x3410)
#define AO_SUBCTRL_AUTOLF_IDLE_CNT_REG                    (AO_SUBCTRL_BASE + 0x3414)
#define AO_SUBCTRL_AUTOLF_FORCE_BUSY_LEVEL2_REG           (AO_SUBCTRL_BASE + 0x3420)
#define AO_SUBCTRL_AUTOLF_FORCE_IDLE_LEVEL2_REG           (AO_SUBCTRL_BASE + 0x3424)
#define AO_SUBCTRL_AUTOLF_IDLE_IN_TH_LEVEL2_REG           (AO_SUBCTRL_BASE + 0x3428)
#define AO_SUBCTRL_AUTOLF_CFG_EN_LEVEL2_REG               (AO_SUBCTRL_BASE + 0x342C)
#define AO_SUBCTRL_AUTOLF_IDLE_STATUS_LEVEL2_REG          (AO_SUBCTRL_BASE + 0x3430)
#define AO_SUBCTRL_AUTOLF_IDLE_CNT_LEVEL2_REG             (AO_SUBCTRL_BASE + 0x3434)
#define AO_SUBCTRL_SC_PWR_SEQ_CTRL_REG                    (AO_SUBCTRL_BASE + 0x3440)
#define AO_SUBCTRL_SC_HOT_RESET_HIPCIEC_CTRL_REG          (AO_SUBCTRL_BASE + 0x3444)
#define AO_SUBCTRL_SC_PERST_CTRL_REG                      (AO_SUBCTRL_BASE + 0x3448)
#define AO_SUBCTRL_SC_HISS_CORE_SEC_CTRL_REG              (AO_SUBCTRL_BASE + 0x3458)
#define AO_SUBCTRL_SC_JA_HEART_BEAT_NUM_REG               (AO_SUBCTRL_BASE + 0x345C)
#define AO_SUBCTRL_SC_JA_CTRL_REG                         (AO_SUBCTRL_BASE + 0x3460)
#define AO_SUBCTRL_SC_JTAG_AUTH_RESULT0_REG               (AO_SUBCTRL_BASE + 0x3464)
#define AO_SUBCTRL_SC_JTAG_AUTH_RESULT1_REG               (AO_SUBCTRL_BASE + 0x3468)
#define AO_SUBCTRL_SC_JTAG_AUTH_RESULT_EN_REG             (AO_SUBCTRL_BASE + 0x346C)
#define AO_SUBCTRL_SC_TOP2HISS_INT_MASK_0_REG             (AO_SUBCTRL_BASE + 0x3470)
#define AO_SUBCTRL_SC_TOP2HISS_INT_MASK_1_REG             (AO_SUBCTRL_BASE + 0x3474)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_0_REG              (AO_SUBCTRL_BASE + 0x3478)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_1_REG              (AO_SUBCTRL_BASE + 0x347C)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_2_REG              (AO_SUBCTRL_BASE + 0x3480)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_3_REG              (AO_SUBCTRL_BASE + 0x3484)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_4_REG              (AO_SUBCTRL_BASE + 0x3488)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_5_REG              (AO_SUBCTRL_BASE + 0x348C)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_6_REG              (AO_SUBCTRL_BASE + 0x3490)
#define AO_SUBCTRL_SC_LP2HISS_INT_MASK_7_REG              (AO_SUBCTRL_BASE + 0x3494)
#define AO_SUBCTRL_SC_TPM_INT_REG                         (AO_SUBCTRL_BASE + 0x34A0)
#define AO_SUBCTRL_SC_TPM_INT_MASK_GIC_REG                (AO_SUBCTRL_BASE + 0x34A4)
#define AO_SUBCTRL_SC_TPM_INT_MASK_HISS_REG               (AO_SUBCTRL_BASE + 0x34A8)
#define AO_SUBCTRL_SC_OS_TIMER_CLK_SEL_REG                (AO_SUBCTRL_BASE + 0x34B0)
#define AO_SUBCTRL_SC_TIMER0_CLK_SEL_REG                  (AO_SUBCTRL_BASE + 0x34B4)
#define AO_SUBCTRL_SC_TIMER1_CLK_SEL_REG                  (AO_SUBCTRL_BASE + 0x34B8)
#define AO_SUBCTRL_SC_TIMER2_CLK_SEL_REG                  (AO_SUBCTRL_BASE + 0x34BC)
#define AO_SUBCTRL_SC_TIMER3_CLK_SEL_REG                  (AO_SUBCTRL_BASE + 0x34C0)
#define AO_SUBCTRL_SC_LP_TIMER0_CLK_SEL_REG               (AO_SUBCTRL_BASE + 0x34C4)
#define AO_SUBCTRL_SC_LP_TIMER1_CLK_SEL_REG               (AO_SUBCTRL_BASE + 0x34C8)
#define AO_SUBCTRL_SC_LP_TIMER2_CLK_SEL_REG               (AO_SUBCTRL_BASE + 0x34CC)
#define AO_SUBCTRL_SC_LP_TIMER3_CLK_SEL_REG               (AO_SUBCTRL_BASE + 0x34D0)
#define AO_SUBCTRL_SC_OS_TIMER_EN_EXTERNAL_REG            (AO_SUBCTRL_BASE + 0x34D4)
#define AO_SUBCTRL_SC_TIMER0_EN_EXTERNAL_REG              (AO_SUBCTRL_BASE + 0x34D8)
#define AO_SUBCTRL_SC_TIMER1_EN_EXTERNAL_REG              (AO_SUBCTRL_BASE + 0x34DC)
#define AO_SUBCTRL_SC_TIMER2_EN_EXTERNAL_REG              (AO_SUBCTRL_BASE + 0x34E0)
#define AO_SUBCTRL_SC_TIMER3_EN_EXTERNAL_REG              (AO_SUBCTRL_BASE + 0x34E4)
#define AO_SUBCTRL_SC_LP_TIMER0_EN_EXTERNAL_REG           (AO_SUBCTRL_BASE + 0x34E8)
#define AO_SUBCTRL_SC_LP_TIMER1_EN_EXTERNAL_REG           (AO_SUBCTRL_BASE + 0x34EC)
#define AO_SUBCTRL_SC_LP_TIMER2_EN_EXTERNAL_REG           (AO_SUBCTRL_BASE + 0x34F0)
#define AO_SUBCTRL_SC_LP_TIMER3_EN_EXTERNAL_REG           (AO_SUBCTRL_BASE + 0x34F4)
#define AO_SUBCTRL_SC_SFC_MEM_DAW_ADDR_REG                (AO_SUBCTRL_BASE + 0x3500)
#define AO_SUBCTRL_SC_SFC_MEM_DAW_SIZE_ID_REG             (AO_SUBCTRL_BASE + 0x3504)
#define AO_SUBCTRL_SC_LSADC0_CTRL_REG                     (AO_SUBCTRL_BASE + 0x3510)
#define AO_SUBCTRL_SC_LSADC1_CTRL_REG                     (AO_SUBCTRL_BASE + 0x3514)
#define AO_SUBCTRL_SC_SDS0_POWER_CTRL_REG                 (AO_SUBCTRL_BASE + 0x3600)
#define AO_SUBCTRL_SC_SDS1_POWER_CTRL_REG                 (AO_SUBCTRL_BASE + 0x3604)
#define AO_SUBCTRL_SC_SDS0_MISC_CTRL_REG                  (AO_SUBCTRL_BASE + 0x3608)
#define AO_SUBCTRL_SC_SDS1_MISC_CTRL_REG                  (AO_SUBCTRL_BASE + 0x360C)
#define AO_SUBCTRL_SC_REPAIR_LOAD_RSTN_REG                (AO_SUBCTRL_BASE + 0x38C0)
#define AO_SUBCTRL_SC_SMMU_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5300)
#define AO_SUBCTRL_SC_I2C4_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5308)
#define AO_SUBCTRL_SC_I2C5_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5310)
#define AO_SUBCTRL_SC_I2C6_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5318)
#define AO_SUBCTRL_SC_I2C9_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5320)
#define AO_SUBCTRL_SC_SPI_ICG_ST_REG                      (AO_SUBCTRL_BASE + 0x5328)
#define AO_SUBCTRL_SC_SMBUS_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5330)
#define AO_SUBCTRL_SC_GPIO_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5338)
#define AO_SUBCTRL_SC_UART_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5340)
#define AO_SUBCTRL_SC_GPIO8_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5348)
#define AO_SUBCTRL_SC_SYSCNT_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5350)
#define AO_SUBCTRL_SC_PMBUS0_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5358)
#define AO_SUBCTRL_SC_PMBUS1_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5360)
#define AO_SUBCTRL_SC_PMCTRL_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5368)
#define AO_SUBCTRL_SC_PMPWM_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5370)
#define AO_SUBCTRL_SC_8K_ICG_ST_REG                       (AO_SUBCTRL_BASE + 0x5378)
#define AO_SUBCTRL_SC_WDOG0_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5380)
#define AO_SUBCTRL_SC_WDOG1_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5388)
#define AO_SUBCTRL_SC_WDOG2_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5390)
#define AO_SUBCTRL_SC_WDOG3_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5398)
#define AO_SUBCTRL_SC_WDOG4_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x53A0)
#define AO_SUBCTRL_SC_WDOG5_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x53A8)
#define AO_SUBCTRL_SC_TIMER0_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x53B0)
#define AO_SUBCTRL_SC_TIMER1_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x53B8)
#define AO_SUBCTRL_SC_GICD_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x53C0)
#define AO_SUBCTRL_SC_ITS_ICG_ST_REG                      (AO_SUBCTRL_BASE + 0x53C8)
#define AO_SUBCTRL_SC_MBIGEN_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x53D0)
#define AO_SUBCTRL_SC_LP_TIMER1_ICG_ST_REG                (AO_SUBCTRL_BASE + 0x53D8)
#define AO_SUBCTRL_SC_LP_TIMER2_ICG_ST_REG                (AO_SUBCTRL_BASE + 0x53E0)
#define AO_SUBCTRL_SC_LP_TIMER3_ICG_ST_REG                (AO_SUBCTRL_BASE + 0x53E8)
#define AO_SUBCTRL_SC_SEC_TIMER_ICG_ST_REG                (AO_SUBCTRL_BASE + 0x53F0)
#define AO_SUBCTRL_SC_SEC_WDOG_ICG_ST_REG                 (AO_SUBCTRL_BASE + 0x53F8)
#define AO_SUBCTRL_SC_IPC_S_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5400)
#define AO_SUBCTRL_SC_IPC_NS_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5408)
#define AO_SUBCTRL_SC_TRNG_ICG_ST_REG                     (AO_SUBCTRL_BASE + 0x5410)
#define AO_SUBCTRL_SC_TIMER2_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5418)
#define AO_SUBCTRL_SC_TIMER3_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5420)
#define AO_SUBCTRL_SC_LP_TIMER0_ICG_ST_REG                (AO_SUBCTRL_BASE + 0x5428)
#define AO_SUBCTRL_SC_LSADC_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5430)
#define AO_SUBCTRL_SC_PAD_DB_ICG_ST_REG                   (AO_SUBCTRL_BASE + 0x5438)
#define AO_SUBCTRL_SC_DJTAG_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5440)
#define AO_SUBCTRL_SC_FUNC_MBIST_ICG_ST_REG               (AO_SUBCTRL_BASE + 0x5448)
#define AO_SUBCTRL_SC_PROBE_ICG_ST_REG                    (AO_SUBCTRL_BASE + 0x5450)
#define AO_SUBCTRL_SC_ITS_RESET_ST_REG                    (AO_SUBCTRL_BASE + 0x54C8)
#define AO_SUBCTRL_SC_MBIGEN_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x54D0)
#define AO_SUBCTRL_SC_GICD_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x54D8)
#define AO_SUBCTRL_SC_I2C4_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5A00)
#define AO_SUBCTRL_SC_I2C5_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5A08)
#define AO_SUBCTRL_SC_I2C6_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5A10)
#define AO_SUBCTRL_SC_I2C9_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5A18)
#define AO_SUBCTRL_SC_SPI_RESET_ST_REG                    (AO_SUBCTRL_BASE + 0x5A20)
#define AO_SUBCTRL_SC_SMBUS_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5A28)
#define AO_SUBCTRL_SC_GPIO_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5A30)
#define AO_SUBCTRL_SC_UART_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5A38)
#define AO_SUBCTRL_SC_GPIO8_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5A40)
#define AO_SUBCTRL_SC_APB_SUBCTRL_RESET_ST_REG            (AO_SUBCTRL_BASE + 0x5A48)
#define AO_SUBCTRL_SC_SYSCNT_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5A50)
#define AO_SUBCTRL_SC_PMCTRL_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5A60)
#define AO_SUBCTRL_SC_PMBUS0_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5A68)
#define AO_SUBCTRL_SC_PMBUS1_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5A70)
#define AO_SUBCTRL_SC_PMPWM_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5A78)
#define AO_SUBCTRL_SC_8K_RESET_ST_REG                     (AO_SUBCTRL_BASE + 0x5A80)
#define AO_SUBCTRL_SC_WDOG0_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5A88)
#define AO_SUBCTRL_SC_WDOG1_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5A90)
#define AO_SUBCTRL_SC_WDOG2_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5A98)
#define AO_SUBCTRL_SC_WDOG3_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5AA0)
#define AO_SUBCTRL_SC_WDOG4_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5AA8)
#define AO_SUBCTRL_SC_WDOG5_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5AB0)
#define AO_SUBCTRL_SC_TIMER0_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5AB8)
#define AO_SUBCTRL_SC_TIMER1_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5AC0)
#define AO_SUBCTRL_SC_TIMER2_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5AC8)
#define AO_SUBCTRL_SC_TIMER3_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5AD0)
#define AO_SUBCTRL_SC_LP_TIMER0_RESET_ST_REG              (AO_SUBCTRL_BASE + 0x5AD8)
#define AO_SUBCTRL_SC_LP_TIMER1_RESET_ST_REG              (AO_SUBCTRL_BASE + 0x5AE0)
#define AO_SUBCTRL_SC_LP_TIMER2_RESET_ST_REG              (AO_SUBCTRL_BASE + 0x5AE8)
#define AO_SUBCTRL_SC_LP_TIMER3_RESET_ST_REG              (AO_SUBCTRL_BASE + 0x5AF0)
#define AO_SUBCTRL_SC_SEC_TIMER_RESET_ST_REG              (AO_SUBCTRL_BASE + 0x5AF8)
#define AO_SUBCTRL_SC_SEC_WDOG_RESET_ST_REG               (AO_SUBCTRL_BASE + 0x5B00)
#define AO_SUBCTRL_SC_IPC_S_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5B08)
#define AO_SUBCTRL_SC_IPC_NS_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5B10)
#define AO_SUBCTRL_SC_TRNG_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5B18)
#define AO_SUBCTRL_SC_BISR_RESET_ST_REG                   (AO_SUBCTRL_BASE + 0x5B38)
#define AO_SUBCTRL_SC_PAD_DB_RESET_ST_REG                 (AO_SUBCTRL_BASE + 0x5B40)
#define AO_SUBCTRL_SC_DJTAG_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5B48)
#define AO_SUBCTRL_SC_FUNC_MBIST_RESET_ST_REG             (AO_SUBCTRL_BASE + 0x5B50)
#define AO_SUBCTRL_SC_LSADC_RESET_ST_REG                  (AO_SUBCTRL_BASE + 0x5B58)
#define AO_SUBCTRL_SC_GIC_NOCMT_ST_REG                    (AO_SUBCTRL_BASE + 0x6000)
#define AO_SUBCTRL_SC_SMBUS_ST_REG                        (AO_SUBCTRL_BASE + 0x6010)
#define AO_SUBCTRL_SC_LSADC0_ST_REG                       (AO_SUBCTRL_BASE + 0x6014)
#define AO_SUBCTRL_SC_LSADC1_ST_REG                       (AO_SUBCTRL_BASE + 0x6018)
#define AO_SUBCTRL_SC_HISS_SYSTEM_STATE_REG               (AO_SUBCTRL_BASE + 0x6020)
#define AO_SUBCTRL_SC_HISS_CORE_STATE_REG                 (AO_SUBCTRL_BASE + 0x6024)
#define AO_SUBCTRL_SC_POWER_ON_TRAP0_REG                  (AO_SUBCTRL_BASE + 0x8000)
#define AO_SUBCTRL_SC_POWER_ON_TRAP1_REG                  (AO_SUBCTRL_BASE + 0x8004)
#define AO_SUBCTRL_SC_PAD_UPDATE_MODE_N_REG               (AO_SUBCTRL_BASE + 0x8008)
#define AO_SUBCTRL_SC_RST_CNT0_REG                        (AO_SUBCTRL_BASE + 0xC110)
#define AO_SUBCTRL_SC_RST_CNT1_REG                        (AO_SUBCTRL_BASE + 0xC114)
#define AO_SUBCTRL_SC_RST_CNT2_REG                        (AO_SUBCTRL_BASE + 0xC118)
#define AO_SUBCTRL_SC_RST_CNT3_REG                        (AO_SUBCTRL_BASE + 0xC11C)
#define AO_SUBCTRL_SC_CRG_DFX_REG                         (AO_SUBCTRL_BASE + 0xC124)
#define AO_SUBCTRL_SC_MRB_HARD_REPAIR_DONE_REG            (AO_SUBCTRL_BASE + 0xE07C)
#define AO_SUBCTRL_SC_EFUSE_HARD_REPAIR_DONE_REG          (AO_SUBCTRL_BASE + 0xE080)
#define AO_SUBCTRL_SC_LAST_RST_STATUS_REG                 (AO_SUBCTRL_BASE + 0xE090)
#define AO_SUBCTRL_SC_SYSCTRL_LOCK_REG                    (AO_SUBCTRL_BASE + 0xF100)
#define AO_SUBCTRL_SC_SYSCTRL_UNLOCK_REG                  (AO_SUBCTRL_BASE + 0xF110)
#define AO_SUBCTRL_SC_IOMUX_TZPC0_REG                     (AO_SUBCTRL_BASE + 0xF114)
#define AO_SUBCTRL_SC_IOMUX_TZPC1_REG                     (AO_SUBCTRL_BASE + 0xF118)
#define AO_SUBCTRL_SC_PROBE_MUX_SEL_REG                   (AO_SUBCTRL_BASE + 0xF200)
#define AO_SUBCTRL_SC_SMMU_ICG_EN_SRST_REQ_SWITCHER_REG   (AO_SUBCTRL_BASE + 0xF300)
#define AO_SUBCTRL_SC_MBIGEN_ICG_EN_SRST_REQ_SWITCHER_REG (AO_SUBCTRL_BASE + 0xF304)
#define AO_SUBCTRL_SC_ITS_ICG_EN_SRST_REQ_SWITCHER_REG    (AO_SUBCTRL_BASE + 0xF308)
#define AO_SUBCTRL_SC_GICD_ICG_EN_SRST_REQ_SWITCHER_REG   (AO_SUBCTRL_BASE + 0xF30C)
#define AO_SUBCTRL_SC_SEC_SWITCH_WDOG0_REG                (AO_SUBCTRL_BASE + 0xF318)
#define AO_SUBCTRL_SC_SEC_SWITCH_WDOG1_REG                (AO_SUBCTRL_BASE + 0xF31C)
#define AO_SUBCTRL_SC_SEC_SWITCH_WDOG2_REG                (AO_SUBCTRL_BASE + 0xF320)
#define AO_SUBCTRL_SC_SEC_SWITCH_WDOG3_REG                (AO_SUBCTRL_BASE + 0xF324)
#define AO_SUBCTRL_SC_SEC_SWITCH_WDOG4_REG                (AO_SUBCTRL_BASE + 0xF328)
#define AO_SUBCTRL_SC_SEC_SWITCH_WDOG5_REG                (AO_SUBCTRL_BASE + 0xF32C)
#define AO_SUBCTRL_SC_SEC_SWITCH_TIMER0_REG               (AO_SUBCTRL_BASE + 0xF340)
#define AO_SUBCTRL_SC_SEC_SWITCH_TIMER1_REG               (AO_SUBCTRL_BASE + 0xF344)
#define AO_SUBCTRL_SC_SEC_SWITCH_TIMER2_REG               (AO_SUBCTRL_BASE + 0xF348)
#define AO_SUBCTRL_SC_SEC_SWITCH_TIMER3_REG               (AO_SUBCTRL_BASE + 0xF34C)
#define AO_SUBCTRL_SC_SEC_SWITCH_LP_TIMER0_REG            (AO_SUBCTRL_BASE + 0xF350)
#define AO_SUBCTRL_SC_SEC_SWITCH_LP_TIMER1_REG            (AO_SUBCTRL_BASE + 0xF354)
#define AO_SUBCTRL_SC_SEC_SWITCH_LP_TIMER2_REG            (AO_SUBCTRL_BASE + 0xF358)
#define AO_SUBCTRL_SC_SEC_SWITCH_LP_TIMER3_REG            (AO_SUBCTRL_BASE + 0xF35C)
#define AO_SUBCTRL_SC_SEC_SWITCH_I2C4_REG                 (AO_SUBCTRL_BASE + 0xF360)
#define AO_SUBCTRL_SC_SEC_SWITCH_I2C5_REG                 (AO_SUBCTRL_BASE + 0xF364)
#define AO_SUBCTRL_SC_SEC_SWITCH_I2C6_REG                 (AO_SUBCTRL_BASE + 0xF368)
#define AO_SUBCTRL_SC_SEC_SWITCH_I2C9_REG                 (AO_SUBCTRL_BASE + 0xF36C)
#define AO_SUBCTRL_SC_SEC_SWITCH_LP_PMBUS0_REG            (AO_SUBCTRL_BASE + 0xF370)
#define AO_SUBCTRL_SC_SEC_SWITCH_LP_PMBUS1_REG            (AO_SUBCTRL_BASE + 0xF374)
#define AO_SUBCTRL_SC_SEC_SWITCH_GPIO8_REG                (AO_SUBCTRL_BASE + 0xF378)
#define AO_SUBCTRL_SC_SEC_SWITCH_SMBUS_REG                (AO_SUBCTRL_BASE + 0xF37C)
#define AO_SUBCTRL_SC_SEC_SWITCH_TPM_REG                  (AO_SUBCTRL_BASE + 0xF380)
#define AO_SUBCTRL_SC_SEC_SWITCH_TOP2HISS_REG             (AO_SUBCTRL_BASE + 0xF384)
#define AO_SUBCTRL_SC_SEC_SWITCH_LP2HISS_REG              (AO_SUBCTRL_BASE + 0xF388)
#define AO_SUBCTRL_SC_ECO_RSV0_REG                        (AO_SUBCTRL_BASE + 0xFF00)
#define AO_SUBCTRL_SC_ECO_RSV1_REG                        (AO_SUBCTRL_BASE + 0xFF04)
#define AO_SUBCTRL_SC_ECO_RSV2_REG                        (AO_SUBCTRL_BASE + 0xFF08)
#define AO_SUBCTRL_SC_ECO_RSV3_REG                        (AO_SUBCTRL_BASE + 0xFF0C)
#define AO_SUBCTRL_SC_ECO_RSV4_REG                        (AO_SUBCTRL_BASE + 0xFF10)
#define AO_SUBCTRL_SC_ECO_RSV5_REG                        (AO_SUBCTRL_BASE + 0xFF14)
#define AO_SUBCTRL_SC_VER_NUM_REG                         (AO_SUBCTRL_BASE + 0xFFFC)

#endif // __AO_SUBCTRL_REG_OFFSET_H__
